I. Field
The present disclosure generally relates to a combined arithmetic logic and shifting device for use in a processor. More particularly, the disclosure relates to a load/store unit that includes an address generation unit having an arithmetic logic unit and a shifting device.
II. Description of Related Art
Advances in technology have resulted in smaller and more powerful personal computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and IP telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can include a web interface that can be used to access the Internet. As such, these wireless telephones include significant computing capabilities.
Typically, as these devices include greater functionality, more internal components may be needed to support the various functions of the devices. Further, as the number of internal components increase, the costs associated with manufacturing the devices increases. For example, a processor within a particular device may execute a variety of computer execution instructions in order to provide the functionality associated with the particular device. Certain instructions, e.g., load/store instructions, may utilize an address generation unit in order to generate a data cache address for loading or storing data. Other instructions may be executed by an execution unit, such as a multiplier or an arithmetic logic unit.
Accordingly, it would be advantageous to provide an improved load/store unit and an enhanced address generation unit within processors.